
REV. 0
AD5532
–5–
SERIAL INTERFACE TIMING DIAGRAMS
1
2
3
4
5
6
7
8
9
10
t
1
t
2
t
3
t
4
t
5
t
6
MSB
LSB
SCLK
SYNC
D
IN
Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)
1
2
3
4
5
t
1
t
2
t
3
t
4
LSB
t
5
t
6
21
22
23
24
MSB
SCLK
SYNC
D
IN
t
11
1
Figure 4. 24-Bit Write (DAC Mode)
t
10
2
t
1
t
2
1
3
4
5
6
7
8
9
10
11
12
13
14
t
7
t
4
t
8
t
9
MSB
LSB
SCLK
SYNC
D
OUT
10
Figure 5. 14-Bit Read (Both Readback Modes)